The present invention relates to semiconductor devices including a multi-line-by-multi-stage shift register circuit, and particularly relates to testing thereof at its actual speed.
Recently, the operation speed of a semiconductor device is increasing more and more. As one kind of function circuits composing the semiconductor device, a multi-line multi-stage shift register circuit composed of flip-flop circuits arranged in matrix is operated at an actual speed of several hundred MHz, for example. A technique for testing the shift register circuit at the actual speed is demanded.
A memory error check system is disclosed in Japanese Unexamined Patent Application Publication 4-107757 as a storage circuit testing technique. This memory error check system includes: a memory for storing the same data as an upper half of a word and a lower half of the word; an expected value storage register for reading out the upper half data at a first timing and temporarily storing it as an expected value; a circuit for reading out the lower half data at a second timing subsequent to the first timing; and a comparator circuit for comparing the read out lower half data and the upper half data stored in the expected value storage register, wherein the comparison result is used as memory error check information.
The above conventional testing technique necessitates the expected value storage register as an additional dedicated component for testing to increase the circuit scale. In the case where the above conventional testing technique is applied to testing on the multi-line multi-stage shift register circuit, an increase in circuit scale (area) of the shift register circuit accompanies apparent wiring delay to invite difficulty in high speed testing at an actual speed of, for example, several hundred MHz.